this datasheet contains new product information. anachip corp. re serves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. rev. 1.0 dec 16, 2004 1/10 peel? 18lv8z-25 / i-35 cmos programmable electric ally erasable logic device features ? low voltage, ultra low power operation - vcc = 2.7 to 3.6 v - icc = 5 a (typical) at standby - icc = 1.5 ma (typical) at 1 mhz - meets jedec lv interface spec (jedsd8-a) - 5 volts tolerant inputs and i/o?s ? cmos electrically erasable technology - superior factory testing - reprogrammable in plastic package - reduces retrofit and development costs ? application versatility - replaces random logic - super set of standard plds - pin and jedec compatible with 16v8 - ideal for battery powered systems - replaces expensive oscillators ? architectural flexibility - enhanced architecture fits in more logic - 113 product terms x 36 input and array - 10 inputs and 8 i/o pins - 12 possible macrocell configurations - asynchronous clear, synchronous preset - independent output enables - programmable clock; pin 1 or p-term - programmable clock polarity - 20 pin dip/soic/tssop and plcc - schmitt triggers on clock and data inputs ? schmitt trigger inputs - eliminates external schmitt trigger devices - ideal for encoder designs general description the peel18lv8z is a programmable electrically erasable logic (peel) spld (simple programmable logic device) that operates over the suppl y voltage range of 2.7v-3.6v and features ultra-low, aut omatic "zero" power-down operation. the peel18lv8z is logically and functionally similar to anachip's 5v peel18cv8 and peel18cv8z. the "zero power" (25 a max. icc) power-down mode makes the peel18lv8z ideal for a broad range of battery- powered portable equipment applications, from hand-held meters to pcmcia modems. ee-reprogrammability provides both the convenience of fast reprogramming for product development and quick product personalization in manufacturing, including engineering change orders. the differences between the peel18lv8z and peel18cv8 include the addition of programmable clock polarity, p-term clock, and schmitt trigger input buffers on all inputs, including the clock. schmitt trigger inputs allow direct input of slow or noisy signals. like the peel18cv8, the peel18lv8z is a logical superset of the industry standard pal16v8 spld. the peel18lv8z provides additional ar chitectural features that allow more logic to be incorporated into the design. anachip's jedec file translat or allows easy conversion of existing 20 pin pld designs to the peel18lv8z architecture without the need for redesign. the peel18lv8z architecture allows it to replace over twenty standard 20-pin dip, soic, tssop and plcc packages. dip i/clk1 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 i 9 gnd 10 11 i 12 i/o v cc 20 i/o 19 i/o 18 i/o 17 i/o 16 i/o 15 i/o 14 i/o 13 1 i/clk1 2 i 3 i 4 i 5 i 6 i 7 i 8 i 9 i 10 gnd 20 v cc 19 i/o 18 i/o 17 i/o 16 i/o 15 i/o 14 i/o 13 i/o tssop 12 i/o 11 i 1 i/clk1 2 i 3 i 4 i 5 i 6 i 7 i 8 i 9 i 10 gnd 20 v cc 19 i/o 18 i/o 17 i/o 16 i/o 15 i/o 14 i/o 13 i/o soic 12 i/o 11 i 4 i 5 i 6 i 7 i 8 i 9 i 10 gnd 11 i 12 i/o 13 i/o 3 i/o 2 i/o 1 i/clk1 vcc 19 i/o plcc-j 18 i/o 17 i/o 16 i/o 15 i/o 14 i/o 20 figure 1 - pin configuration clk mux (optional) a figure 2 - block diagram not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 2/10 i/ c lk* i* i* i* i* i* i* i* i* i* (o p tio na l) * schmitt trigger inputs figure 3 - peel18lv8z logic array diagram not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 3/10 function description the peel18lv8z implements logic functions as sum-of- products expressions in a programmable-and/fixed-or logic array. programming the connections of input signals into the array creates user-defined functions. user- configurable output structures in the form of i/o macrocells further increase logic flexibility. architecture overview the peel18lv8z architecture is illustrated in the block diagram of figure 14. ten dedicated inputs and 8 i/os provide up to 18 inputs and 8 outputs for creation of logic functions. at the core of the device is a programmable electrically erasable and array that drives a fixed or array. with this structure, the pe el18lv8z can implement up to 8 sum-of-products logic expressions. associated with each of the 8 or functions is an i/o macrocell that can be independently programmed to one of 12 different configurations. the programmable macrocells allow each i/o to be used to create sequential or combinatorial logic functions of active-high or active-low polarity, while providing three different feedback paths into the and array. and/or logic array the programmable and array of the peel18lv8z (shown in figure 15) is formed by input lines intersecting product terms. the input lines and product terms are used as follows: ? 36 input lines: - 20 input lines carry the true and complement of the signals applied to the 10 input pins - 16 additional lines carry the true and complement values of feedback or input signals from the 8 i/os ? 113 product terms: - 102 product terms are used to form sum of product functions - 8 output enable terms (one for each i/o) - 1 global synchronous preset term - 1 global asynchronous clear term - 1 programmable clock term at each input-line/product-term intersection, there is an eeprom memory cell that det ermines whether or not there is a logical connection at that intersection. each product term is essentially a 36-input and gate. a product term that is connected to bot h the true and complement of an input signal will always be false and thus will not affect the or function that it drives. when all the connections on a product term are opened, a "don't care" state exists and that te rm will always be true. when programming the peel18lv8z, the device programmer first performs a bulk erase to remove the previous pattern. the erase cycle opens every logical connection in the array. the device is configured to perform the user-defined function by programming selected connections in the and array. (note that peel device programmers automatically program all of the connections on unused product terms so that they will have no effect on the output function). variable product term distribution the peel18lv8z provides 113 product terms to drive the 8 or functions. these product terms are distributed among the outputs in groups of 8, 10, 12, 14, and 16 to form logical sums (see figure 15). this distribution allows optimum use of the device resources. programmable i/o macrocell the unique twelve-configuration output macrocell provides complete control over the architecture of each output. the ability to configure each output independently lets you to tailor the configuration of the peel18lv8z to the precise requirements of your design. macrocell architecture each i/o macrocell, as shown in figure 4, consists of a d- type flip-flop and two signal-select multiplexers. the four eeprom bits controlling these multiplexers determine the configuration of each macroc ell. these bits determine output polarity, output type (r egistered or non-registered) and input-feedback path (bidirectional i/o, combinatorial feedback). refer to table 1 for details. equivalent circuits for the tw elve macrocell configurations are illustrated in figure 5. in addition to emulating the four pal-type output structures (confi gurations 3, 4, 9, and 10), the macrocell provides eight additional configurations. when creating a peel device design, the desired macrocell configuration is generally specified explicitly in the design file. when the design is assembled or compiled, the macrocell configuration bits are defined in the last lines of the jedec programming file. output type the signal from the or array can be fed directly to the output pin (combinatorial functi on) or latched in the d-type flip-flop (registered function). the d-type flip-flop latches data on the rising edge of the cl ock and is controlled by the global preset and clear te rms. when the synchronous preset term is satisfied, the q output of the register is set high at the next rising edge of the clock input. satisfying not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 4/10 the asynchronous clear sets q low, regardless of the clock state. if both terms are satisfied simultaneously, the clear will override the preset. output polarity each macrocell can be configured to implement active-high or active-low logic. programmable polarity eliminates the need for external inverters. output enable the output of each i/o macrocell can be enabled or disabled under the control of its associated programmable output enable product term. when the logical conditions programmed on the output enable term are satisfied, the output signal is propagated to the i/o pin. otherwise, the output buffer is switched into the high-impedance state. under the control of the output enable term, the i/o pin can function as a dedicated input, a dedicated output, or a bi- directional i/o. opening every connection on the output enable term will permanently enable the output buffer and yield a dedicated output. conversely, if every connection is intact, the enable term will always be logically false and the i/o will function as a dedicated input. input/feedback select the peel18lv8z macrocell also provides control over the feedback path. the input/feedback signal associated with each i/o macrocell can be obtained from three different locations; from the i/o input pin, from the q output of the flip-flop (registered feedback), or directly from the or gate (combinatorial feedback). bi-directional i/o the input/feedback signal is ta ken from the i/o pin when using the pin as a dedicated input or as a bi-directional i/o. (note that it is possible to create a registered output function with a bi-directional i/o, refer to figure 4). figure 4 - peel18lv8z i/o macro cell combinatorial feedback the signal-select multiplexer gives the macrocell the ability to feedback the output of t he or gate, bypassing the output buffer, regardless of whether the output function is registered or combinatorial. this feature allows the creation of asynchronous latches, even when the output must be disabled. (refer to configuratio ns 5, 6, 7, and 8 in figure 5.) registered feedback feedback also can be taken from the register, regardless of whether the output function is programmed to be combinatorial or registered. when implementing a combinatorial output function, registered feedback allows for the internal latching of states without giving up the use of the external output. programmable clock options a unique feature of the peel18lv8z is a programmable clock multiplexer that allows the user to select true or complement forms of either input pin or product-term clock sources. operates in both 3 volt and 3.3 volt systems the peel18lv8z is designed to operate with a v cc range of 2.7 to 3.6 volts d.c. this allows operation in both 3 volt 10% (battery operated) and 3.3 volt 10% (power supply operated) systems. t he propagation delay t pd is 5 ns slower at the lower voltage, but this is typically not an issue in battery-operated systems (see - a.c. electrical characteristicstable 1 - absolute maximum ratings- a.c. electrical characteristics). schmitt trigger inputs the peel18lv8z has schmitt trigger input buffers on all inputs, including the clock. schmitt trigger inputs allow direct input of slow signals such as biomedical and sine waves or clocks. they are also useful in cleaning up noisy signals. this makes the peel18lv8z especially desirable in portable applications where the environment is less predictable. zero power feature the cmos peel18lv8z features "zero-power" standby operation for ultra-low power consumption. with the "zero- power" feature, transition-detection circuitry monitors the inputs, i/os (including clk) and feedbacks. if these signals do not change for a period of time greater than approximately three t pd 's, the outputs are latched in their current state and the device automatically powers down. when the next signal transition is detected, the device will "wake up" for active operation until the signals stop not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 5/10 switching long enough to trigger the next power-down. (note that the tpd is approximately 5 ns. slower on the first transition from sleep mode.) as a result of the "zero-powe r" feature, significant power savings can be realized for combinatorial or sequential operations when the inputs or clock change at a modest rate. see figure 6. when the peel18lv8z is powered up, a built-in feature holds the outputs in tri-state until vcc reaches 2.2v. this prevents output transitions during power-up. figure 5 - equivalent circuits for the twelve configurations of the peel18lv8z i/o macrocell configuration # a b c d input/feedback select output select 1 0 0 1 0 active low 2 1 0 1 0 register active high 3 0 1 0 0 active low 4 1 1 0 0 bi-directional i/o combinatorial active high 5 0 0 1 1 active low 6 1 0 1 1 register active high 7 0 1 1 1 active low 8 1 1 1 1 combinatorial feedback combinatorial active high 9 0 0 0 0 active low 10 1 0 0 0 register active high 11 0 1 1 0 active low 12 1 1 1 0 register feedback combinatorial active high not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 6/10 0.01 0.1 1 10 100 0.01 0.1 1 10 100 frequency in mhz icc in ma figure 6 - typical icc vs. input clock frequency for the 18lv8z design security the peel18lv8z provides a special eeprom security bit that prevents unauthorized readi ng or copying of designs programmed into the device. the pld programmer sets the security bit, either at the conclusion of the programming cycle or as a separate step, after the device has been programmed. once the security bit is set it is impossible to verify (read) or program t he peel until the entire device has first been erased with the bulk-erase function. signature word the signature word feature allows a 64-bit code to be programmed into the peel18lv8z if the software option is used. the code can be read back even after the security bit has been set. the signature word can be used to identify the pattern programmed into the device or to record the design revision, etc. programming support anachip's jedec file translat or allows easy conversion of existing 20 pin pld designs to the peel18lv8z, without the need for redesign. anachip also offers (for free) its proprietary winplace software, an easy-to-use entry level pc-based software development system. programming support includes all the popular third party programmers such as bp microsystems, system general, logical devices, and numerous others. not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 7/10 this device has been designed and tested for the specified operating ranges. improper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may cause permanent damage. table 1 - absolute maximum ratings symbol parameter conditions rating unit v cc supply voltage relative to ground -0.5 to + 6.0 v v i , v o voltage applied to any pin 2 relative to ground 1 -0.5 to 5.5 v i o output current per pin (i ol , i oh ) 25 ma t st storage temperature -65 to +150 c t lt lead temperature soldering 10 seconds +300 c table 2 - operating range symbol parameter conditions min max unit vcc supply voltage 3 commercial / industrial 2.7 3.6 v commercial 0 +70 ta ambient temperature industrial -40 +85 c t rvcc v cc rise time see note 4 250 ms table 3 - d. c. electrical characteristics over the operating range ( unless otherwise specified) symbol parameter conditions min max unit v oh output high voltage - ttl v cc = min, i oh = -2.0 ma v cc - 0.5 v v ohc output high voltage - cmos v cc = min, i oh = -10 a v cc - 0.3 v v ol output low voltage - ttl v cc = min, i ol = 8.0 ma 0.4 v v olc output low voltage - cmos v cc = min, i ol = 10 a 0.15 v v ih input high voltage v cc = 3.3 v 2.0 5.5 v v il input low voltage v cc = 3.3 v -0.3 0.8 v v h input voltage hysteresis 0.2 v v cc = max, gnd v in v cc , i/o = high z +/- 1 a input leakage current v cc = min, gnd v in 5.5v, i/o = high z 25 a v cc = max, gnd v in v cc , i/o = high z +/- 1 a i in i/o leakage current v cc = min, gnd v in 5.5v, i/o = high z 500 a i ccs v cc current, standby vin = 0v or v cc , all outputs disabled 5 5 (typ) 25 a i cc 11 v cc current, f=1mhz vin = 0v or v cc , all outputs disabled 5 1.5 (typ) 3 ma c in 8 input capacitance 6 pf c out 8 output capacitance ta = 25c, vcc = max @ f = 1 mhz 12 pf not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 8/10 table 4 - a.c. electrical characteristics over the operating range 9 -25 i-35 3v 10% 3.3v 10% 3v 10% 3.3v 10% symbol parameter min max min max min max min max units tpd input 6 to non-registered output in continuous mode 13 30 25 40 35 ns toe input 6 to output enable 7 30 25 40 35 ns tod input 6 to output disable 7 30 25 40 35 ns tco1 clock to output 20 15 28 25 ns tco2 clock to comb output delay via internal registered feedback 40 35 56 49 ns tcf clock to feedback 14 9 20 13 ns tsc input 6 or feedback setup to clock 20 15 28 21 ns thc input 6 hold after clock 0 0 0 0 ns tcl, tch clock low time, clock high time 9 20 13 28 18 ns tcp min clock period ext (tsc + tco1 ) 40 30 56 39 ns fmax1 internal feedback 1/ (tsc + tcf) 12 29.4 41.6 20.8 29.4 mhz fmax2 external feedback (1/ tcp) 12 25 33.3 17.9 25.6 mhz fmax3 no feedback 1/ (tcl + tch) 12 25 38.4 17.9 27.7 mhz taw asynchronous reset pulse width 30 25 40 35 ns tap input to asynchronous reset 30 25 40 35 ns tar asynchronous reset recovery time 30 25 40 35 ns treset power-on reset time for registers in clear state 14 5 5 5 5 s inputs i/o, registered feedback, synchronous preset clock asynchronous reset registered outputs combinatorial outputs figure 7 - switching waveforms notes: 1. minimum dc input is -0.5v, however, inputs may undershoot to -2.0v for periods less than 20 ns. 2. v i and v o are not specified for program / verify operation. 3. the supply voltage range of 2.7 to 3.6v was chosen to allow this part to be used in both 3v 10% and 3.3v 10% applications. 4. test points for clock and vcc in t r and t f are referenced at the 10% and 90% levels. 5. i/o pins are 0v and v cc . 6. "input" refers to an input pin signal. 7. t oe is measured from input transition to v ref 0.1v, t od is measured from input transition to v oh -0.1v or v ol +0.1v; v ref =v l. 8. capacitances are tested on a sample basis. 9. test conditions assume: signal transition times of 3ns or less from the 10% and 90% points, timing reference levels of 1.5v (unless otherwise specified). 10. test one output at a time for duration of less than 1 second. 11. i cc for a typical application: this parameter is tested with the device programmed as an 8-bit counter. 12. parameters are not 100% tested. specifications are based on initial characterization and are tested after any design process modification that might affect operational frequency. 13. t pd , t oe , t od , t co , t sc , and t ap are approximately 5 ns. slower on the first transaction from sleep mode. 14. all inputs at gnd. not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 9/10 thevenin equivalent standard load 3.15v output output c l r1 r2 r l c l v l figure 8 - peel? device and array test loads technology r1 r2 rl vl cl cmos 284 k ? 258 k ? 113 k ? 1.275v 33 pf ttl 308 ? 433 ? 180 ? 1.840v 33 pf ordering information part number speed temperature package peel18lv8zp-25 (l) 25ns commercial 20-pin plastic dip peel18lv8zpi-35 (l) 35ns industrial 20-pin plastic dip peel18lv8zj-25 (l) 25ns commercial 20-pin plcc peel18lv8zji-35 (l) 35ns industrial 20-pin plcc peel18lv8zs-25 (l) 25ns commercial 20-pin soic peel18lv8zsi-35 (l) 35ns industrial 20-pin soic peel18lv8zt-25 (l) 25ns commercial 20-pin tssop peel18lv8zti-35 (l) 35ns industrial 20-pin tssop part number peel tm 18lv8z pi-35x package p = 20-pin plastic 300 mil dip s = 20-pin soic 300 mil gullwing temperature range (blank) = commercial 0 to 70 o c speed lead free blank : normal l : lead free package j = 20-pin plastic (j) leaded chip carrier (plcc) suffix device t = 20-pin tssop 170mil i = industrial -40 to 85 o c -25 = 25ns tpd -35 = 35ns tpd not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 10/10 anachip corp. head office , 2f, no. 24-2, industry e. rd. iv, science-based industrial park, hsinchu, 300, taiwan tel: +886-3-5678234 fax: +886-3-5678368 anachip usa 780 montague expressway, #201 san jose, ca 95131 tel: (408) 321-9600 fax: (408) 321-9696 email: sales_usa@anachip.com website: http://www.anachip.com ?2004 anachip corporation anachip reserves the right to make changes in specifications at any time and without notice. the information furnished by anachip in this publication is believed to be accurate and re liable. however, there is no responsibility assumed by anachip for its use nor for any infringements of pat ents or other rights of third parties resu lting from its use. no license is granted under any patents or patent rights of anachip. anachip?s produc ts are not authorized for use as critical components in life support devices or systems. marks bearing ? or ? are registered trademarks and trademarks of anachip corp. not recommended for new designs - contact factory for availability
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